The present invention generally relates to system having a combined system, memory, and graphic controller, and more specifically to a system and graphic controller using a unified memory.
Prior art computer systems have traditionally used separate system and graphics memory controllers. One reason for using separate system and graphic controllers has been the need to use dedicated graphics memory, which was controlled by the graphic controller. The use of dedicated graphics memory has been needed in order to access and process graphics data fast enough to assure the frame refresh rate of the computer system is maintained. When a video graphics engine can not maintain a frame rate, the picture can look choppy and will generally be unsuitable for viewing by a user.
With three-dimensional graphics, multiple data types are stored for each pixel. In order to render the final image on a display device, it is necessary of a graphics engine to retrieve all types of data associated with each pixel. Often, this involves opening and closing multiple blocks of memory, requiring overhead delay in the process.
Prior art graphic systems have also used Accelerated Graphics Port (AGP) protocol in order to access translation table information to map graphics data requests from virtual memory space to logical memory space. The implementation of the AGP requires the entire protocol associated with the AGP port to be completely implemented not only on the memory controller, but on the external device also being accessed via the AGP port as well. As a result, the amount of overhead needed to satisfy the AGP protocol requirements increases the cost of the system.
Yet another problem associated with prior art systems was that the system bus was used to access memory and hard drive devices resulting in bandwidth limitation of the system bus. For example, a Peripheral Components Interconnect (PCI) bus would often be used in order to access system memory and peripherals, as well as other mass storage devices. When the PCI bus was used to transmit data from a number of data storage sources, the arbiter associated with the external storage devices became bandwidth limited due to the transmission capabilities of the protocol implemented on the system bus.
Therefore, a system capable of overcoming these problems would be advantageous.